Architectures and Arithmetic for Low Static Power Consumption in Nanoscale CMOS

<table class="table-group" id="tab10"><tr><td><table class="table"><tr><td class="thead-hr" colspan="2"><hr/></td></tr><tr class="thead"><td align="left">12-bit Filter</td><td align="center">336/793 = 0.42</td></tr><tr><td class="thead-hr" colspan="2"><hr/></td></tr><tr><td align="left">24-bit Filter</td><td align="center">592/1586 = 0.37</td></tr><tr class="table-tr"><td colspan="2"><hr class="tbody-hr"/></td></tr></table></td></tr></table>

VLSI Design

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Table 10

Table 10: Architectures and Arithmetic for Low Static Power Consumption in Nanoscale CMOS 