Architectures and Arithmetic for Low Static Power Consumption in Nanoscale CMOS

Table 2

The simulated static power consumption.

FA (nW)	Reg. (nW)	AND (nW)	HA (nW)	Inv. (nW)
𝑃FA=11.2	𝑃reg=7.1	𝑃and=1.9	𝑃HA=3.7	𝑃inv=0.9