Architectures and Arithmetic for Low Static Power Consumption in Nanoscale CMOS

<table class="table-group" id="tab7"><tr><td><table class="table"><tr><td class="thead-hr" colspan="2"><hr/></td></tr><tr class="thead"><td align="left">Bit-Serial Filter</td><td align="center">1178/2017 = 0.58</td></tr><tr><td class="thead-hr" colspan="2"><hr/></td></tr><tr><td align="left">2-Bit Digit-Serial Filter</td><td align="center">1421/2017 = 0.70</td></tr><tr class="table-tr"><td colspan="2"><hr class="tbody-hr"/></td></tr></table></td></tr></table>

Static power ratio in the complete 12-bit filters.

VLSI Design

tab7

Table 7

Table 7: Architectures and Arithmetic for Low Static Power Consumption in Nanoscale CMOS 