Architectures and Arithmetic for Low Static Power Consumption in Nanoscale CMOS

<table class="table-group" id="tab9"><tr><td><table class="table"><tr><td class="thead-hr" colspan="2"><hr/></td></tr><tr class="thead"><td align="left">12-bit filter arithmetic</td><td align="center">81/538 = 0.15</td></tr><tr><td class="thead-hr" colspan="2"><hr/></td></tr><tr><td align="left">24-bit filter arithmetic</td><td align="center">81/1075 = 0.075</td></tr><tr class="table-tr"><td colspan="2"><hr class="tbody-hr"/></td></tr></table></td></tr></table>

Static power ratio in the arithmetic part of the IIR-filter.

VLSI Design

tab9

Table 9

Table 9: Architectures and Arithmetic for Low Static Power Consumption in Nanoscale CMOS 