VLSI Design

VLSI Design / 2009 / Article / Tab 2

Research Article

Networks-On-Chip Based on Dynamic Wormhole Packet Identity Mapping Management

Table 2

Number of slices of the router with WF routing on a Virtex2 FPGA device.

Flit sizeFB depth = 4FB depth = 8Overhead

16 + 6 bits2809366230.37%
24 + 6 bits3136438039.67%
32 + 6 bits3468500944.43%

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