VLSI Design

VLSI Design / 2009 / Article / Tab 3

Research Article

Networks-On-Chip Based on Dynamic Wormhole Packet Identity Mapping Management

Table 3

Logic synthesis of router prototypes with adaptive routing algorithms (flit size: 32 + 6 bits, FIFO depth: 4).

Router's routing Alg.WFOEELNF

Num. of logic cells7149713271197206
Total cell area ( )0.10580.10570.10540.1064

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