VLSI Design

VLSI Design / 2009 / Article / Tab 4

Research Article

Networks-On-Chip Based on Dynamic Wormhole Packet Identity Mapping Management

Table 4

Logic synthesis of the router prototype with static XY routing algorithm (flit size: 32 + 6 bits) using UMC 130-nm and 180-nm standard-cell technologies.

130-nm techn.FIFO depth: 2FIFO depth: 4

Num. of logic cells53636661
Total cell area ( )0.07670.1018
Max. Freq. (MHz)472453

180-nm techn.FIFO depth: 2FIFO depth: 4

Num. of logic cells50336572
Total cell area ( )0.1230.168
Max. freq. (MHz)264247

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