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VLSI Design
Volume 2011 (2011), Article ID 178516, 19 pages
http://dx.doi.org/10.1155/2011/178516
Review Article

Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications

1Department of Information Technology, VLSI Design Laboratory, ABV-Indian Institute of Information Technology and Management, Madhya Pradesh, Gwalior 474010, India
2School of Studies in Physics, Jiwaji University, Madhya Pradesh, Gwalior 474011, India

Received 9 September 2010; Revised 11 January 2011; Accepted 11 March 2011

Academic Editor: A. G. M. Strollo

Copyright © 2011 Subhra Dhar et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [3 citations]

The following is the list of published articles that have cited the current article.

  • Mirgender Kumar, Sarvesh Dubey, Pramod Kumar Tiwari, and S. Jit, “Analytical Modeling and Simulation of Subthreshold Characteristics of Back-Gated SSGOI and SSOI MOSFETs: A Comparative Study,” Current Applied Physics, 2013. View at Publisher · View at Google Scholar
  • Vijay Kumar Sharma, and Manisha Pattanaik, “Techniques For Low Leakage Nanoscale Vlsi Circuits: A Comparative Study,” Journal of Circuits, Systems and Computers, pp. 1450061, 2014. View at Publisher · View at Google Scholar
  • G. Conti, S. Nemšák, C.-T. Kuo, M. Gehlmann, C. Conlon, A. Keqi, A. Rattanachata, O. Karslıoğlu, J. Mueller, J. Sethian, H. Bluhm, J. E. Rault, J. P. Rueff, H. Fang, A. Javey, and C. S. Fadley, “Characterization of free-standing InAs quantum membranes by standing wave hard x-ray photoemission spectroscopy,” APL Materials, vol. 6, no. 5, pp. 058101, 2018. View at Publisher · View at Google Scholar