Table of Contents
VLSI Design
Volume 2011, Article ID 178516, 19 pages
Review Article

Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications

1Department of Information Technology, VLSI Design Laboratory, ABV-Indian Institute of Information Technology and Management, Madhya Pradesh, Gwalior 474010, India
2School of Studies in Physics, Jiwaji University, Madhya Pradesh, Gwalior 474011, India

Received 9 September 2010; Revised 11 January 2011; Accepted 11 March 2011

Academic Editor: A. G. M. Strollo

Copyright © 2011 Subhra Dhar et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [7 citations]

The following is the list of published articles that have cited the current article.

  • Varun Goel, Anuj Kumar Maurya, Sanjay Sharma, and Sanjay Kumar, “Study of role of channel engineering and gate engineering in silicon-on-insulator (SOI) MOSFETs using 2-D analytical modeling,” 2016 3rd International Conference on Emerging Electronics (ICEE), pp. 1–5, . View at Publisher · View at Google Scholar
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