Review Article

Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications

Table 1

Technology scaling rules for three cases [8].

Physical parametersConstant electric field scaling factorGeneralized scaling factorGeneralized selective scaling factor

Channel length, insulator thickness1/α1/α1/α d
Wiring width, channel width1/α1/α1/α w
Electric field in device1εε
Voltage1/αε/αε/α d
On-current per device1/αε/αε/α d
Dopingαεαεα d
Area1/α 21/α 21/ 𝛼 2 𝑤
Capacitance1/α1/α1/α w
Gate delay1/α1/α1/α d
Power dissipation1/α 2ε 2/α 2ε 2/α wα d
Power density1ε 2ε 2α w/α d