Table of Contents
VLSI Design
Volume 2011, Article ID 407507, 12 pages
Research Article

CONTANGO: Integrated Optimization of SoC Clock Networks

EECS Department, University of Michigan, 2260 Hayward Street, Ann Arbor, MI 48109-2121, USA

Received 26 November 2010; Accepted 20 January 2011

Academic Editor: Rached Tourki

Copyright © 2011 Dong-Jin Lee and Igor L. Markov. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


On-chip clock networks are remarkable in their impact on the performance and power of synchronous circuits, in their susceptibility to adverse effects of semiconductor technology scaling, as well as in their strong potential for improvement through better CAD algorithms and tools. Existing literature is rich in ideas and techniques but performs large-scale optimization using analytical models that lost accuracy at recent technology nodes and have rarely been validated by realistic SPICE simulations on large industry designs. Our work offers a methodology for SPICE-accurate optimization of clock networks, coordinated to satisfy slew constraints and achieve best tradeoffs between skew, insertion delay, power, as well as tolerance to variations. Our implementation, called Contango, is evaluated on 45 nm benchmarks from IBM Research and Texas Instruments with up to 50 K sinks. It outperforms all published results in terms of skew and shows superior scalability.