CONTANGO: Integrated Optimization of SoC Clock Networks

Figure 2

Key steps of the Contango methodology. Blue boxes represent skew reduction techniques, red octilinear shapes show CLR reductions, and the green box with thick border reduces both objectives. An Improvement- and violation-checking (IVC) step follows each clock-network evaluation (CNE) using circuit simulation tools, for example, SPICE. “Fail” indicates no improvement or having slew violations, leading to a transition to the next optimization.