CONTANGO: Integrated Optimization of SoC Clock Networks

Table 7

Scalability on Texas Instruments benchmarks. The “Latency” column represents maximum 1.2 V latencies. SPICE runs are counted in parenthesis.

# sinks	CLR, ps	Skew, ps	Latency, ps	Cap., pF	⌚, min
200	13.47	2.124	506.8	52.21	2.2 (21)
500	14.84	2.174	528.0	99.53	6.28 (20)
1 K	17.53	3.138	543.1	162.3	12.5 (20)
2 K	16.56	3.136	543.9	276.1	19.3 (15)
5 K	23.20	3.853	538.5	591.1	99.6 (22)
10 K	25.54	5.562	538.0	1130	352.8 (23)
20 K	32.47	10.46	546.8	2243	1867 (35)
50 K	31.52	8.774	545.1	5243	16027 (45)