Journals
Publish with us
Publishing partnerships
About us
Blog
VLSI Design
Table of Contents
Special Issues
VLSI Design
/
2011
/
Article
/
Fig 12
/
Review Article
The Impact of Statistical Leakage Models on Design Yield Estimation
Figure 12
Due to leakages, the RBL may falsely discharge causing false evaluate of node
𝑁
0
.
(a)
(b)
(c)