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VLSI Design
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2011
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Article
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Fig 8
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Research Article
A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies
Figure 8
Scatter plot of the constructed models.
(a)
Scatter plot of estimated and original values for the noise model with normalized test data
(b)
Scatter plot of estimated and original values for the power model with normalized test data
(c)
Scatter plot of estimated and original values for the impedance model with normalized test data