A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies

Table 3

Grid search technique using hold-out method.

Model	𝜎^2	𝛾	ARE (%)		𝑅		𝑇tr
			Training	Test	Training	Test	(min)
𝜌1	3.43	173.26	1.82	2.48	0.999	0.998	118.19
𝜌2	2.10	112.04	2.32	4.18	0.918	0.905	117.83
𝜌3	5.43	387.55	2.02	3.14	0.999	0.937	118.13