Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints

<table>Sizing factor to achieve 20% delay increase as <svg height="15.80625" id="M243" style="vertical-align:-3.2316pt" version="1.1" viewbox="0 0 27.001249 15.80625" width="27.001249" xmlns="http://www.w3.org/2000/svg">
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<tspan style="font-size: 12.50px; " x="0" y="0">A</tspan>
<tspan style="font-size: 12.50px; " x="9.0272522" y="0">F</tspan>
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<tspan style="font-size: 8.75px; " x="0" y="0">𝑏</tspan>
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</svg> increases, the sizing factor of gates 1 and 2 is increased, while the sizing factor of gates 5 and 6 is decreased.</table>

VLSI Design

fig11

Figure 11

Figure 11: Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints 