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VLSI Design
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2011
/
Article
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Fig 2
/
Research Article
Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints
Figure 2
EDG and hardware intensity. Note that when (
𝐷
,
𝐸
) → (
𝐷
0
,
𝐸
0
), hardware intensity and EDG converge.