Table of Contents
VLSI Design
Volume 2013, Article ID 103473, 15 pages
Research Article

A Generic Three-Sided Rearrangeable Switching Network for Polygonal FPGA Design

1Department of Computer Science and Information Engineering, National Taiwan Ocean University, 2 Pei-Ning Road, Keelung 202-24, Taiwan
2Department of Electronic Engineering, National Ilan University, 1, Sec. 1, Shen-Lung Road, I-Lan 260, Taiwan
3Department of Electronic Engineering, China University of Science and Technology, 245, Sec. 3, Academia Road, Nangang District, Taipei City 115, Taiwan

Received 5 August 2013; Accepted 27 September 2013

Academic Editor: Wen-Jyi Hwang

Copyright © 2013 Mao-Hsu Yen et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


We propose a new Polygonal Field Programmable Gate Array (PFPGA) that consists of many logic blocks interconnected by a generic three-stage three-sided rearrangeable polygonal switching network (PSN). The main component of this PSN consists of a polygonal switch block interconnected by crossbars. In comparing our PSN with a three-stage three-sided clique-based (Xilinx 4000-like FPGAs) (Palczewski; 1992) switching network of the same size and with the same number of switches, we find that the three-stage three-sided clique-based switching network is not rearrangeable. Also, the effects of the rearrangeable structure and the number of terminals on the network switch-efficiency are explored and a proper set of parameters is determined to minimize the number of switches. Moreover, we explore the effect of the PSN structure and granularity of cluster logic blocks on the switch efficiency of PFPGA. Experiments on benchmark circuits show that switches and speed performance are significantly improved. Based on experiment results, we can determine the parameters of PFPGA for the VLSI implementation.