A Generic Three-Sided Rearrangeable Switching Network for Polygonal FPGA Design

Figure 10

(a), (b) An RRV (1_1,3, 0, 0, 0, 1_1,7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1_3,7, 0, 0, 0, 0, 0) routable on a PSB_SU(2,2,2,4).

(a)

(b)