A Generic Three-Sided Rearrangeable Switching Network for Polygonal FPGA Design

Figure 4

(a) A polygonal switch block PSB_𝐶(𝑚,𝑠_𝑝,𝑠_𝑜,𝑠_𝑖) with 𝑚=2, 𝑠_𝑝=2, 𝑠_𝑜=2, and 𝑠_𝑖=4; and (b) Its correspondence to two PSB_𝐶(1,2,2,4).