Table of Contents
VLSI Design
Volume 2013, Article ID 103473, 15 pages
http://dx.doi.org/10.1155/2013/103473
Research Article

A Generic Three-Sided Rearrangeable Switching Network for Polygonal FPGA Design

1Department of Computer Science and Information Engineering, National Taiwan Ocean University, 2 Pei-Ning Road, Keelung 202-24, Taiwan
2Department of Electronic Engineering, National Ilan University, 1, Sec. 1, Shen-Lung Road, I-Lan 260, Taiwan
3Department of Electronic Engineering, China University of Science and Technology, 245, Sec. 3, Academia Road, Nangang District, Taipei City 115, Taiwan

Received 5 August 2013; Accepted 27 September 2013

Academic Editor: Wen-Jyi Hwang

Copyright © 2013 Mao-Hsu Yen et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. J. Rose and S. Brown, “Flexibility of interconnection structures for field-programmable gate arrays,” IEEE Journal of Solid-State Circuits, vol. 26, no. 3, pp. 277–282, 1991. View at Publisher · View at Google Scholar · View at Scopus
  2. S. Franchini, A. Gentile, F. Sorbello, G. Vassallo, and S. Vitabile, “An embedded, FPGA-based computer graphics coprocessor with native geometric algebra support,” Integration, the VLSI Journal, vol. 42, no. 3, pp. 346–355, 2009. View at Publisher · View at Google Scholar · View at Scopus
  3. S. D. Brown, R. J. Francis, J. Rose, and Z. G. Vranesic, Field-Programmable Gate Arrays, Kluwer Academic, 1992.
  4. V. E. Benes, “On rearrangeable three-stage connecting networks,” Bell System Technical Journal, vol. 41, no. 5, pp. 1481–1492, 1962. View at Google Scholar
  5. Y. M. Yen and T. Y. Feng, “On a class of rearrangeable networks,” IEEE Transactions on Computers, vol. 41, no. 11, pp. 1361–1379, 1992. View at Publisher · View at Google Scholar
  6. C. Mitchell and P. Wild, “One-stage one-sided rearrangeable switching networks,” IEEE Transactions on Communications, vol. 37, no. 1, pp. 52–56, 1989. View at Google Scholar · View at Scopus
  7. A. Varma and S. Chalasani, “Reduction of crosspoints in one-sided crosspoint switching networks,” in Proceedings of the 8th Annual Conference of the IEEE Computer and Communications Societies. Technology: Emerging or Converging? (INFOCOM '89), vol. 3, pp. 943–952, Ottawa, Canada, April 1989. View at Scopus
  8. J. Gordon and S. Srikanthan, “Single sided switching networks,” Electronics Letters, vol. 26, no. 4, pp. 248–250, 1990. View at Google Scholar · View at Scopus
  9. Y.-W. Chang, D. F. Wong, and C. K. Wong, “Universal switch modules for fpga design,” ACM Transactions on Design Automation of Electronic Systems, vol. 1, no. 1, pp. 80–101, 1996. View at Google Scholar · View at Scopus
  10. G. M. Wu, M. Shyu, and Y. -W. Chang, “Universal switch blocks for three-dimensional FPGA design,” in Proceedings of the ACM International Symposium on Field Programmable Gate Arrays (FPGA '99), Monterey, Calif, USA, February 1999.
  11. M. Shyu, G.-M. Wu, Y.-D. Chang, and Y.-W. Chang, “Generic universal switch blocks,” IEEE Transactions on Computers, vol. 49, no. 4, pp. 348–359, 2000. View at Publisher · View at Google Scholar · View at Scopus
  12. H. Fan, J. Liu, Y.-L. Wu, and C. K. Wong, “Reduction design for generic universal switch blocks,” ACM Transactions on Design Automation of Electronic Systems, vol. 7, no. 4, pp. 526–546, 2002. View at Publisher · View at Google Scholar · View at Scopus
  13. M.-H. Yen, C. Yu, H.-Y. Shin, and S.-J. Chen, “A three-sided rearrangeable switching network for a binary fat tree,” International Journal of Electronics, vol. 98, no. 6, pp. 713–734, 2011. View at Publisher · View at Google Scholar · View at Scopus
  14. M. H. Yen, M. C. Shie, and S. H. Lan, “Polygonal routing network for FPGA/FPIC,” in Proceedings of the International Symposium on VLSI Technology, System, and Applications (VLSI-TSA '99), pp. 104–107, 1999.
  15. M.-H. Yen, S.-J. Chen, and S. H. Lan, “Symmetric and programmable multi-chip module for low-power prototyping system,” VLSI Design, vol. 12, no. 2, pp. 113–124, 2001. View at Google Scholar · View at Scopus
  16. M.-H. Yen, S.-J. Chen, and S. H. Lan, “A three-stage one-sided rearrangeable polygonal switching network,” IEEE Transactions on Computers, vol. 50, no. 11, pp. 1291–1294, 2001. View at Publisher · View at Google Scholar · View at Scopus
  17. J. Rose, R. J. Francis, D. Lewis, and P. Chow, “Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency,” IEEE Journal of Solid-State Circuits, vol. 25, no. 5, pp. 1217–1225, 1990. View at Publisher · View at Google Scholar · View at Scopus
  18. V. Betz and J. Rose, “Cluster-based logic blocks for FPGAs: area-efficiency vs. input sharing and size,” in Proceedings of the IEEE Custom Integrated Circuits Conference (CICC '97), pp. 551–554, Santa Clara, Calif, USA, May 1997. View at Scopus
  19. M. Marek-Sadowska, “Switch box routing: a retrospective,” Integration, the VLSI Journal, vol. 13, no. 1, pp. 39–65, 1992. View at Google Scholar · View at Scopus
  20. W. K. Luk, “A greedy switch-box router,” Integration, the VLSI Journal, vol. 3, no. 2, pp. 129–149, 1985. View at Google Scholar · View at Scopus
  21. J. Pan, Y.-L. Wu, C. K. Wong, and G. Yan, “On the optimal four-way switch box routing structures of FPGA greedy routing architectures,” Integration, the VLSI Journal, vol. 25, no. 2, pp. 137–159, 1998. View at Google Scholar · View at Scopus
  22. G. G. Lemienx and S. D. Brown, “A detailed routing algorithm for allocating wire segments in field-programmable gate arrays,” in Proceedings of the ACM/SIGDA Physical Design Workshop, pp. 215–216, Lake Arrowhead, Calif, USA, 1993.