Table of Contents
VLSI Design
Volume 2013, Article ID 157872, 9 pages
http://dx.doi.org/10.1155/2013/157872
Research Article

Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL

1ECE Department, Hindusthan College of Engineering & Technology, Coimbatore 641 032, India
2Department of Electrical Sciences, Adithya Institute of Technology, Coimbatore 641 107, India
3Maharaja Institute of Technology, Coimbatore 641 407, India
4ECE Department, Coimbatore Institute of Technology, Coimbatore 641 014, India

Received 28 September 2012; Revised 20 January 2013; Accepted 5 February 2013

Academic Editor: Wieslaw Kuzmicz

Copyright © 2013 A. Kishore Kumar et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. A. Kishore Kumar, D. Somasundareswari, V. Duraisamy, and M. Pradeepkumar, “Low power multiplier design using complementary pass-transistor asynchronous adiabatic logic,” International Journal on Computer Science and Engineering, vol. 2, no. 7, pp. 2291–2297, 2010. View at Google Scholar
  2. R. Zimmermann and W. Fichtner, “Low-power logic styles: CMOS versus pass-transistor logic,” IEEE Journal of Solid-State Circuits, vol. 32, no. 7, pp. 1079–1090, 1997. View at Google Scholar · View at Scopus
  3. V. S. K. Bhaaskaran, S. Salivahanan, and D. S. Emmanuel, “Semi-custom design of adiabatic adder circuits,” in Proceedings of the 19th International Conference on VLSI Design Held Jointly with 5th International Conference on Embedded Systems Design, pp. 745–748, January 2006. View at Publisher · View at Google Scholar · View at Scopus
  4. A. Blotti and R. Saletti, “Ultralow-power adiabatic circuit semi-custom design,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 11, pp. 1248–1253, 2004. View at Publisher · View at Google Scholar · View at Scopus
  5. V. G. Oklobdzija, D. Maksimovic, and F. Lin, “Pass-transistor adiabatic logic using single power-clock supply,” IEEE Transactions on Circuits and Systems II, vol. 44, no. 10, pp. 842–846, 1997. View at Google Scholar · View at Scopus
  6. D. Maksimović, V. G. Oklobdzija, B. Nikolic, and K. W. Current, “Clocked CMOS adiabatic logic with integrated single-phase power-clock supply,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, no. 4, pp. 460–463, 2000. View at Publisher · View at Google Scholar · View at Scopus
  7. L. Verga, F. Kovacs, and G. Hosszu, “An improved pass gate adiabatic logic,” in Proceedings of the 14th Annual International ASIC/SOC Conference, pp. 208–211, 2001.
  8. Y. Zhang, H. H. Chen, and J. B. Kuo, “0.8 V CMOS adiabatic differential switch logic circuit using bootstrap technique for low-voltage low-power VLSI,” Electronics Letters, vol. 38, no. 24, pp. 1497–1499, 2002. View at Publisher · View at Google Scholar · View at Scopus
  9. J. Hu, W. Zhang, and Y. Xia, “Complementary pass-transistor adiabatic logic and sequential circuits using three-phase power supply,” in Proceedings of the 47th Midwest Symposium on Circuits and Systems, vol. 2, pp. 201–204, July 2004. View at Scopus
  10. J. Hu, T. Xu, and H. Li, “A lower-power register file based on complementary pass-transistor adiabatic logic,” IEICE Transactions on Information and Systems, vol. E88-D, no. 7, pp. 1479–1485, 2005. View at Publisher · View at Google Scholar · View at Scopus
  11. J. Dai, J. Hu, W. Zhang, and L. Wang, “Adiabatic CPL circuits for sequential logic systems,” in Proceedings of the 49th Midwest Symposium on Circuits and Systems (MWSCAS '06), pp. 713–717, August 2007. View at Publisher · View at Google Scholar · View at Scopus
  12. J. Parkand, S. Je Hong, and J. Kim, “Energy-saving design technique achieved by latched pass-transistor adiabatic logic,” in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS '05), vol. 5, pp. 4693–4696, May 2005. View at Publisher · View at Google Scholar · View at Scopus
  13. A. G. Dickinson and J. S. Denker, “Adiabatic dynamic logic,” IEEE Journal of Solid-State Circuits, vol. 30, no. 3, pp. 311–315, 1995. View at Publisher · View at Google Scholar · View at Scopus
  14. M. Arsalan and M. Shams, “Charge-recovery power clock generators for adiabatic logic circuits,” in Proceedings of the 18th International Conference on VLSI Design: Power Aware Design of VLSI Systems, pp. 171–174, January 2005. View at Scopus
  15. M. Arsalan and M. Shams, “Asynchronous adiabatic logic,” in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS '07), pp. 3720–3723, May 2007. View at Scopus
  16. J. Hu, W. Zhang, X. Ye, and Y. Xia, “Low power adiabatic logic circuits with feedback structure using three-phase power supply,” in Proceedings of the International Conference on Communications, Circuits and Systems, vol. 2, pp. 1375–1379, May 2005. View at Scopus
  17. M. Suzuki, N. Ohkubo, T. Shinbo et al., “1.5-ns 32-b CMOS ALU in double pass-transistor logic,” IEEE Journal of Solid-State Circuits, vol. 28, no. 11, pp. 1145–1151, 1993. View at Publisher · View at Google Scholar · View at Scopus
  18. L. Wang, J. Hu, and J. Dai, “A low-power multiplier using adiabatic CPL circuits,” in Proceedings of the International Symposium on Integrated Circuits (ISIC '07), pp. 21–24, September 2007. View at Publisher · View at Google Scholar · View at Scopus
  19. R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, “Design of ion-implanted MOSFET's with very small physical dimensions,” IEEE Journal of Solid-State Circuits, vol. 9, no. 5, pp. 256–268, 1974. View at Google Scholar · View at Scopus