Verification of Mixed-Signal Systems with Affine Arithmetic Assertions

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="239064.fig.005a" src="https://static.hindawi.com/articles/vlsi/volume-2013/239064/figures/239064.fig.005a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>Accurate diode model</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="239064.fig.005b" src="https://static.hindawi.com/articles/vlsi/volume-2013/239064/figures/239064.fig.005b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>Approximation of accurate model</td></tr></table></td></tr></table>

<table>Forward diode characteristic.</table>

VLSI Design

fig5

Figure 5

Figure 5: Verification of Mixed-Signal Systems with Affine Arithmetic Assertions 