Meta-Algorithms for Scheduling a Chain of Coarse-Grained Tasks on an Array of Reconfigurable FPGAs

Table 1

Two-dimensional array 𝑅 representing the assignment of tasks to FPGAs and board configurations. Each row represents a board configuration and each column represents an FPGA. (Thus, Task 5 is assigned to FPGA 3 in Configuration 2.) Note that tasks are listed in row major order but are not necessarily consecutive. Note also that 𝑡 the number of temporal board configurations is not known a priori.

Board config no.	FPGAs on board
	1	2	3	4
1	1	2	3
2		4	5	6
3	7	8	9	10
⋮
⋮
𝑡			𝑛−1	𝑛