Design Example of Useful Memory Latency for Developing a Hazard Preventive Pipeline High-Performance Embedded-Microprocessor

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="425105.fig.001a" src="https://static.hindawi.com/articles/vlsi/volume-2013/425105/figures/425105.fig.001a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b> Hazard condition</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="425105.fig.001b" src="https://static.hindawi.com/articles/vlsi/volume-2013/425105/figures/425105.fig.001b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>Hazard prevention by inserting NOP</td></tr></table></td></tr></table>

<table>The conventional hazard prevention technique.</table>

VLSI Design

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Figure 1

Figure 1: Design Example of Useful Memory Latency for Developing a Hazard Preventive Pipeline High-Performance Embedded-Microprocessor 