Design Example of Useful Memory Latency for Developing a Hazard Preventive Pipeline High-Performance Embedded-Microprocessor

Table 2

There are more benefits from pipeline Method-2.

Comparison items	Method-1	Method-2
Gate count	69,004	47,100 (−31.7%)
Maximum frequency	18.766 MHz	30.547 MHz (+62.8%)
Maximum net delay	18.140 ns	16.813 ns (−7.3%)