Table of Contents Author Guidelines Submit a Manuscript
VLSI Design
Volume 2013, Article ID 683615, 18 pages
http://dx.doi.org/10.1155/2013/683615
Review Article

Ingredients of Adaptability: A Survey of Reconfigurable Processors

MPSoC Architectures, UMIC Research Centre, RWTH Aachen University, Mies-van-der-Rohe Strasse 15, 52074 Aachen, Germany

Received 18 December 2012; Revised 14 May 2013; Accepted 1 June 2013

Academic Editor: Yann Thoma

Copyright © 2013 Anupam Chattopadhyay. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [25 citations]

The following is the list of published articles that have cited the current article.

  • Denis S. Loubach, “A runtime reconfiguration design targeting avionics systems,” 2016 IEEE/AIAA 35th Digital Avionics Systems Conference (DASC), pp. 1–8, . View at Publisher · View at Google Scholar
  • Li Zhou, Jianfeng Zhang, and Hengzhu Liu, “Ant Colony Algorithm for Steiner Tree Problem in CGRA Mapping,” 2017 4th International Conference on Information Science and Control Engineering (ICISCE), pp. 198–202, . View at Publisher · View at Google Scholar
  • Alexey Platunov, Arkady Kluchev, and Aleksandr Penskoi, “Expanding design space for complex embedded systems with HLD-methodology,” 2014 6th International Congress on Ultra Modern Telecommunications and Control Systems and Workshops (ICUMT), pp. 157–164, . View at Publisher · View at Google Scholar
  • Caio Souza Oliveira, and Diogenes C. da Silva, “Alchemy: An MSP430-based reconfigurable processor architecture,” 2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS), pp. 1–4, . View at Publisher · View at Google Scholar
  • Arkady Kluchev, Alexey Platunov, and Aleksandr Penskoi, “HLD methodology in embedded systems design with a multilevel reconfiguration,” 2014 3rd Mediterranean Conference on Embedded Computing (MECO), pp. 36–39, . View at Publisher · View at Google Scholar
  • Zoltan Endre Rakossy, Axel Acosta-Aponte, Tobias G. Noll, Gerd Ascheid, Rainer Leupers, and Anupam Chattopadhyay, “Design and synthesis of reconfigurable control-flow structures for CGRA,” 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), pp. 1–8, . View at Publisher · View at Google Scholar
  • Youngsoo Kim, Shrikant Jadhav, and Clay S. Gloster, “Dataflow to Hardware Synthesis Framework on FPGAs,” 2016 International Symposium on Computer Architecture and High Performance Computing Workshops (SBAC-PADW), pp. 91–96, . View at Publisher · View at Google Scholar
  • Zoltan Endre Rakossy, Dominik Stengele, Gerd Ascheid, Rainer Leupers, and Anupam Chattopadhyay, “Exploiting scalable CGRA mapping of LU for energy efficiency using the Layers architecture,” 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp. 337–342, . View at Publisher · View at Google Scholar
  • Omid Akbari, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram, and Muhammad Shafique, “PX-CGRA: Polymorphic approximate coarse-grained reconfigurable architecture,” 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 413–418, . View at Publisher · View at Google Scholar
  • Alexander Fell, Zoltán Endre Rákossy, and Anupam Chattopadhyay, “Force-directed scheduling for Data Flow Graph mapping on Coarse-Grained Reconfigurable Architectures,” 2014 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2014, 2014. View at Publisher · View at Google Scholar
  • Bouthaina Damak, Rachid Benmansour, Mouna Baklouti, Mohamed Abid, and Smail Niar, “Design space exploration for customized asymmetric heterogeneous MPSoC,” Proceedings - 2014 17th Euromicro Conference on Digital System Design, DSD 2014, pp. 50–57, 2014. View at Publisher · View at Google Scholar
  • Razvan Nane, Vlad-Mihai Sima, Cuong Pham-Quoc, Fernando Goncalves, and Koen Bertelspp. 138–145, 2014. View at Publisher · View at Google Scholar
  • Anupam Chattopadhyay, and Xiaolin Chen, “A timing driven cycle-accurate simulation for coarse-grained reconfigurable architectures,” Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 9040, pp. 293–300, 2015. View at Publisher · View at Google Scholar
  • Zoltán Endre Rákossy, Dominik Stengele, Axel Acosta-Aponte, Saumitra Chafekar, Paolo Bientinesi, and Anupam Chattopadhyay, “Scalable and efficient linear algebra kernel mapping for low energy consumption on the layers CGRA,” Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 9040, pp. 301–310, 2015. View at Publisher · View at Google Scholar
  • Mohammed El-Shafei, Imtiaz Ahmad, and Mohammad Gh. Alfailakawi, “Implementation of Harmony Search on Embedded Platform,” Microprocessors and Microsystems, 2016. View at Publisher · View at Google Scholar
  • Liang Liu, Viktor Öwall, and Chenxin Zhangpp. 1–195, 2016. View at Publisher · View at Google Scholar
  • P. Garcia, T. Gomes, J. Monteiro, A. Tavares, and M. Ekpanyapong, “On-Chip Message Passing Sub-System for Embedded Inter-Domain Communication,” IEEE Computer Architecture Letters, vol. 15, no. 1, pp. 33–36, 2016. View at Publisher · View at Google Scholar
  • Lorenzo Verdoscia, and Roberto Giorgi, “A Data-Flow Soft-Core Processor for Accelerating Scientific Calculation on FPGAs,” Mathematical Problems in Engineering, vol. 2016, pp. 1–21, 2016. View at Publisher · View at Google Scholar
  • Mansureh Shahraki Moghaddam, Jae-Min Cho, and Kiyoung Choi, “Reconfigurable Architectures,” Handbook of Hardware/Software Codesign, pp. 335–376, 2017. View at Publisher · View at Google Scholar
  • Moghaddam Shahraki Mansureh, Jae-Min Cho, and Kiyoung Choi, “Reconfigurable Architectures,” Handbook of Hardware/Software Codesign, pp. 1–42, 2017. View at Publisher · View at Google Scholar
  • Hasna Bouraoui, Chadlia Jerad, Anupam Chattopadhyay, and Nejib Ben Hadj-Alouane, “Hardware Architectures for Embedded Speaker Recognition Applications,” ACM Transactions on Embedded Computing Systems, vol. 16, no. 3, pp. 1–28, 2017. View at Publisher · View at Google Scholar
  • Artjom Grudnitsky, Lars Bauer, and Jorg Henkel, “Efficient Partial Online Synthesis of Special Instructions for Reconfigurable Processors,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 2, pp. 594–607, 2017. View at Publisher · View at Google Scholar
  • Mohammad Hossein Sargolzaei, and Siamak Mohammadi, “Energy Efficient Configuration Unification and Compression for CGRAs,” Microprocessors and Microsystems, 2018. View at Publisher · View at Google Scholar
  • Alfonso Rodríguez, Juan Valverde, Jorge Portilla, Andrés Otero, Teresa Riesgo, and Eduardo de la Torre, “FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo3 Framework,” Sensors, vol. 18, no. 6, pp. 1877, 2018. View at Publisher · View at Google Scholar
  • Reeba Korah, Salivahanan, and J. Armstrong Joseph, “Efficient string matching FPGA for speed up network Intrusion detection,” Applied Mathematics and Information Sciences, vol. 12, no. 2, pp. 397–404, 2018. View at Publisher · View at Google Scholar