Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic

Table 2

Comparison of power, delay, and PDP of 8-inverter chain with load capacitance at 𝑓_𝑖=1 MHz.

Power dissipation (μW)
Capacitance (fF)	20	30	50	100	200	250	300
CMOS	0.66	0.93	1.4	2.7	5.4	6.8	8.1
QSERL	0.99	1.3	1.8	3.1	5.31	6.31	7.2
IQSERL	0.23	0.35	0.61	1.3	3.34	4.4	5.7
Delay (ns)
CMOS	2.7	4.1	6.6	12.8	24.9	30.9	36.9
QSERL	69.4	73.1	79.2	91	109	117	124
IQSERL	7.18	9.5	13.5	21.8	35	40.8	46.3
PDP (fJ)
CMOS	1.78	3.8	9.24	34.5	134	210	298
QSERL	68.7	95	142	282	578	738	892
IQSERL	1.65	3.32	8.24	28.3	116	179	263