A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures

Table 5

Power saving over fixed-latency implementation having the same operations/second throughput.

Design	𝑉DD value for wanted throughput	Dynamic power saving	Leakage power saving	Total power saving
[2]	0.77 V	36%	77%	44%
This work	0.60 V	78%	89%	81%