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VLSI Design
Volume 2013, Article ID 803616, 6 pages
Research Article

High-Accuracy Programmable Timing Generator with Wide-Range Tuning Capability

Department of Electrical Engineering, National Yunlin University of Science and Technology, No. 123, Section 3, University Road, Douliou, Yunlin County 64002, Taiwan

Received 27 December 2012; Accepted 1 April 2013

Academic Editor: Yeong-Kang Lai

Copyright © 2013 Ting-Li Chu et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


In this paper, a high-accuracy programmable timing generator with wide-range tuning capability is proposed. With the aid of dual delay-locked loop (DLL), both of the coarse- and fine-tuning mechanisms are operated in precise closed-loop scheme to lessen the effects of the ambient variations. The timing generator can provide sub-gate resolution and instantaneous switching capability. The circuit is implemented and simulated in TSMC 0.18 μm 1P6M technology. The test chip area occupies 1.9 mm2. The reference clock cycle can be divided into 128 bins by interpolation to obtain 14 ps resolution with the clock rate at 550 MHz. The INL and DNL are within −0.21~+0.78 and −0.27~+0.43 LSB, respectively.