Table of Contents Author Guidelines Submit a Manuscript
Corrigendum

A corrigendum for this article has been published. To view the corrigendum, please click here.

VLSI Design
Volume 2013, Article ID 803616, 6 pages
http://dx.doi.org/10.1155/2013/803616
Research Article

High-Accuracy Programmable Timing Generator with Wide-Range Tuning Capability

Department of Electrical Engineering, National Yunlin University of Science and Technology, No. 123, Section 3, University Road, Douliou, Yunlin County 64002, Taiwan

Received 27 December 2012; Accepted 1 April 2013

Academic Editor: Yeong-Kang Lai

Copyright © 2013 Ting-Li Chu et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. B. Arkin, “Realizing a production ATE custom processor and timing IC containing 400 independent low-power and high-linearity timing verniers,” in Proceedings of the IEEE International Solid-State Circuits Conference, Digest of Technical Papers (ISSCC '04), pp. 348–349, February 2004. View at Publisher · View at Google Scholar
  2. J. Chapman, J. Currin, and S. Payne, “A low-cost high-performance CMOS timing vernier for ATE,” in Proceedings of the International Test Conference, pp. 459–468, Washington, DC, USA, October 1995. View at Publisher · View at Google Scholar
  3. J. Christiansen, “An integrated CMOS 0.15 ns digital timing generator for TDC's and clock distribution systems,” IEEE Transactions on Nuclear Science, vol. 42, no. 4, pp. 753–757, 1995. View at Publisher · View at Google Scholar
  4. J. Christiansen, “An integrated high resolution CMOS timing generator based on an array of delay locked loops,” IEEE Journal of Solid-State Circuits, vol. 31, no. 7, pp. 952–957, 1996. View at Publisher · View at Google Scholar
  5. J. M. Chou, Y. T. Hsieh, and J. T. Wu, “Phase averaging and interpolation using resistor strings or resistor rings for multi-phase clock generation,” IEEE Transactions on Circuits and Systems I, vol. 53, no. 5, pp. 984–991, 2006. View at Publisher · View at Google Scholar · View at Scopus
  6. K. H. Cheng and Y. L. Lo, “A fast-lock wide-range delay-locked loop using frequency-range selector for multiphase clock generator,” IEEE Transactions on Circuits and Systems II, vol. 54, no. 7, pp. 561–565, 2007. View at Publisher · View at Google Scholar · View at Scopus