LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization

Table 2

Comparison of hardware increase in check node processor and variable processor with synthesis area for the three low power “Methods”. (For the Split-Row Threshold design none of these methods are applied).

Design	Check processor		Variable processor
	Mode Adjust	Synth. Area (𝜇m^2)	Mode Adjust 1	Mode Adjust 2	Synth. Area (𝜇m^2)
Split-Row Threshold	—	3644	—	—	1200
Method 1	8 MUX + 6 AND + 4 OR	4193	8 MUX	18 AND	1270
Method 2	8 AND + 2 OR	3835	5 MUX + 2 AND	12 AND	1258
Method 3	4 MUX + 6 AND	4068	8 MUX	18 AND	1270