Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="984376.fig.0012a" src="https://static.hindawi.com/articles/vlsi/volume-2013/984376/figures/984376.fig.0012a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>Original </td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="984376.fig.0012b" src="https://static.hindawi.com/articles/vlsi/volume-2013/984376/figures/984376.fig.0012b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>Refined</td></tr></table></td></tr></table>

<table>Refining linear estimator by recursion.</table>

VLSI Design

fig12

Figure 12

Figure 12: Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits 