Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits
Figure 15
Failure probability for a “C-element” realisation from 500 versions: (a) without SB, (b) with SB ( from mean), (c) comparison of (a) and (b), and (d) comparison with more accurate estimates of mean and standard deviation used for Pareto-SB.
