Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits

<table>Yield obtained from 3000 transistor-level simulations of SRAM<svg height="11.125" id="M239" style="vertical-align:-0.1638pt" version="1.1" viewbox="0 0 33.974998 11.125" width="33.974998" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
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</svg> for strongly correlated case.</table>

VLSI Design

fig19

Figure 19

Figure 19: Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits 