Research Article
Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits
Table 2
Time saving illustrated by comparing simulations with SB to simulations without SB.
| Circuit | Binary full adder | C-element | Muller pipeline ring | 9 parameters | 12 parameters | 21 parameters |
| Start of tail | 1.5σ | 2σ | 1.5σ | 2σ | 1.5σ | 2σ | 1000 circuit without SB | 215.99 s | 221.34 s | 250.05 s | 288.51 s | 949.59 s | 1003.9 s | 1000 circuit with SB | 6.75 s | 3.96 s | 7.63 s | 4.24 s | 27.17 s | 13.15 s | Time saving | 96.9% | 98.2% | 96.94% | 98.5% | 97.1% | 98.7% |
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