Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool

Algorithm 1

 (1)  n  =  # of rows in W, 𝐷⁰  = W

(2)  for(k=1 to n)

(3)       for(i=1 to n)

(4)           for(j=1 to n)

(5)           𝑑^𝑘_𝑖𝑗  = min𝑑^(𝑘−1)_𝑖𝑗,𝑑^(𝑘−1)_𝑖𝑘+𝑑^(𝑘−1)_𝑖𝑘

(6)           end for

(7)       end for

(8)  end for

(9)  return 𝐷^𝑛