Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool

Algorithm 2

   (1) //Algorithm for computing the critical path

  (2) Input: a DFG of G = (V,E,t,d) Where c is the

  (3) computation time of the node and d

  (4) is the initial delay on edge E

  (5) Output: Critical path C

  (6) Sort all the vertices topologically in the DFG G

  (7) with v fallowing u

  (8) if there is a zero delay edge from  𝑢→𝑣

  (9) For all vertices from the sorted list

(10) If non zero delay on the edge E in G then

 (11) 𝛾_𝑖 = 𝑡_𝑣

(12) else

(13)  𝛾_𝑖 = 𝑡_𝑣 + max(𝛾_𝑖)  ∈  edge  𝑒∶𝑢→𝑣  in  𝐺  with  𝑑_𝑒 = 0

(14) end if;

(15)  𝛾=𝛾₁,𝛾₂,…,𝛾_𝑚

(16) where m = number of entries in the topologically sorted list

(17) end for;

(18) compute  𝛾=max{𝛾}