Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool

Algorithm 3

    (1) Algorithm for computing the shortest path

   (2) Input: a DFG of G = (V,E,t,d) Where c is the computation time of the node and d

   (3) is the initial delay on edge E

   (4) Output: All pair shortest path matrix M

   (5) for i = 1 to N

   (6)  for j = 1 to N

   (7)   if i = j, then

   (8)      M[i,j] = (0,0)

   (9)   else M[i,j] = inf

 (10)  end for

  (11)  end for

 (12)  for all the edges  𝑒∶𝑢→𝑣, 𝑀[𝑢,𝑣]=𝑑  for edge e

 (13)  for  𝑘→1  to N

 (14)   for  𝑖→1  to N

 (15)    for  𝑗→1  to N

 (16)       if  𝑀[𝑖,𝑗]>𝑀[𝑖,𝑘]+𝑀[𝑘,𝑗]

 (17)       M[i,j]  =  M[i,k]  +  M[k,j]

 (18)    end for

 (19)  end for

(20) end for

 (21) Output shortest path matrix M