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VLSI Design
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2014
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Article
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Fig 2
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Research Article
Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits
Figure 2
(a) HS-drain gating, (b) HS-power gating, (c) HS-DHPF, and (d) HS-DFPH.
(a)
(b)
(c)
(d)