Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics

<div>Complete <svg height="12.0395pt" id="M22" style="vertical-align:-2.3616pt" version="1.1" viewbox="-0.0498162 -9.6779 99.3583 12.0395" width="99.3583pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.0135,0,0,-0.0135,0,0)"><path d="M293 -169V-141C218 -131 209 -90 209 -44C209 19 222 85 222 152C222 207 198 255 139 269V273C199 286 222 334 222 388C222 454 209 523 209 588C209 632 218 671 293 681V709C234 709 148 695 148 577C147 513 155 438 155 372C155 337 152 291 64 285V256C152 250 155 204 155 169C156 105 148 31 148 -41C148 -157 234 -169 293 -169Z" id="g113-124"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="347" vert-adv-y="347"></glyph.data></g><g transform="matrix(.0135,0,0,-0.0135,4.701,0)"><path d="M285 378C315 398 338 416 353 432C373 451 384 474 384 503C384 579 325 635 236 635H235C182 635 136 610 108 579L65 516L85 496C110 533 150 575 205 575C258 575 300 543 300 481C300 407 232 369 141 339L147 310C163 315 188 321 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transform="matrix(.0135,0,0,-0.0135,94.248,0)"><path d="M283 255V284C195 290 192 337 192 375C192 436 200 508 200 580C200 696 116 709 54 709V681C127 671 139 634 139 588C138 524 125 452 125 387C125 333 149 286 209 272V268C148 253 125 206 125 151C126 87 139 16 139 -47C139 -92 127 -131 54 -141V-169C115 -169 200 -152 200 -41C200 32 192 104 192 164C192 202 195 249 283 255Z" id="g113-126"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="347" vert-adv-y="347"></glyph.data></g></svg>  × 4-slot structure, showing metal layers only.</div>

VLSI Design

fig16

Figure 16

Figure 16: Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics 