Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics

<div>Suggested abutted multiplexer row/issue slot structure for 4-wide issue. Rows represent issue slots. Core area is ~32 × 11.9 <i>μ</i>m = 378 <i>μ</i>m<sup>2</sup> per bit (top four cells).</div>

VLSI Design

fig18

Figure 18

Figure 18: Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics 