Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics

<div>Issue width versus access time for stack using various implementation schemes. Showing operand access time for operand pairs 1-2, 3-4, 5-6, and 7-8, where operand pairs 1-2 have zero access time.</div>

VLSI Design

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Figure 8

Figure 8: Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics 