Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics

Table 11

Reported register file delay times.

Reference	Ports^a  Tot (R  + W)	(FO4)	(FO4)	Comments
[20, 21]	10 (5 + 5)		22	250 nm CMOS, AMD K7 88 × 90 bit
[20, 22]	8 (4 + 4)	7		130 nmCMOS, 256 × 32 bit
[20, 23]	5 (3 + 2)	7	18	250 nm CMOS, 16 × 64 bit
[20, 24]	5 (3 + 2)	8		250 nm CMOS, 32 × 64 bit, IBM PowerPC
[20, 25]	8	0	13	500 nm CMOS, 32 × 64 bit
[20]	6 (4 + 2)	11	15	32 × 64 bit logical effort model
[20]	9 (6 + 3)	11	16	32 × 64 bit logical effort model
[20]	12	12	17	32 × 128 bit logical effort model
[26]	12 (8 + 4)	17		100 nm CMOS, 16 × 32 bit, low power
[26]	12	8		100 nm CMOS, 16 × 32 bit, high speed
[27]	8 (6 + 2)	5		250 nm SOI, 32 × 64 bits
[28]	12 (4 + 4)	11		100 nm, 160 × 64, two-bank, 440 reg
[28]	12 (4 + 4)	14		100 nm, 160 × 64, two-bank, 80 reg
[28]	24 (16 + 8)	15		100 nm, 160 × 64, two-bank, 40 reg
[28]	24 (16 + 8)	21		100 nm, 160 × 64, two-bank, 80 reg
[29]	17	18		1 um CHMOS, 128 × 64 bit,
[30]	14 (10 + 4)	19		400 nm, 116 × 64 bit
[31]	16 (10 + 6)	23		110 nm CMOS, 34 × 64 bit
[32]	24 (16 + 8)	23		130 nm, 512 reg
[33]	10	10	16	80 × 64 bit, various 250–35 nm
[34]	16 (12 + 4)	15		75 nm CMOS, 128 register,
[35]	2 (1 + 1)	11		180 nm, 160 reg 8 bank
[35]	2 (1 + 1)	10		180 nm, 160 reg 4 bank
[35]	8 (4 + 4)	15		180 nm, 160 reg, 1 bank
[35]	8 (4 + 4)	12		180 nm, 100 reg, 1 bank
[35]	8 (4 + 4)	10		180 nm, 60 reg, 1 bank
[35]	8 (4 + 4)	10		180 nm, 60 reg, 4 bank
[36]	5 (3 + 2)		19	500 nm CMOS, 128 reg
[36]	6 (3 + 3)		20	500 nm CMOS, 128 reg
[36]	7 (4 + 3)		21	500 nm CMOS, 128 reg
[36]	8 (4 + 4)		22	500 nm CMOS, 128 reg
[37]	12 (8 + 4)		14	500 nm CMOS, 48 reg,
[37]	12 (8 + 4)		16	500 nm CMOS, 96 reg

Ports are stated as T (R + W) where T is port total, and bracketed figures (R + W) represent read and write ports where known.
^bDelays are stated as FO4 delay, assuming 1 FO4 delay equates to an approximation scale of 2 nm per ps [38].