Journals
Publish with us
Publishing partnerships
About us
Blog
VLSI Design
Table of Contents
Special Issues
VLSI Design
/
2014
/
Article
/
Tab 6
/
Research Article
Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics
Table 6
Access times.
IW
CEN
CEI
MEN
MEI
TNN
1
0 ps
0 ps
0 ps
0 ps
0 ps
0
0
0
0
0
2
291 ps
211 ps
225 ps
168 ps
125 ps
6
5
5
4
3
3
582 ps
422 ps
450 ps
336 ps
250 ps
6/13
5/9
5/10
4/7
3/5
4
873 ps
633 ps
675 ps
504 ps
375 ps
6/13/19
5/9/14
5/10/15
4/7/11
3/5/8
FO4 delays shown beneath for issues slots 2/3/4.