Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics
Table 8
(a) Timing models, various simulation modes. (b) Simulation timings for TNN multiplexer driving various next stages. (c) Schematic timings for LATCH and TAG-MUX components.
(a)
Mux
Data sheet
Schematic
Cell + wire
With bus
3m1
107 ps
121 ps
136 ps
156 ps
4m1
116 ps
134 ps
155 ps
176 ps
5m1
125 ps
150 ps
172 ps
195 ps
(b)
3m1
4m1
5m1
FO5C
156 ps
176 ps
195 ps
(3.4)
(3.9)
(4.3)
FO1T
127 ps
144 ps
159 ps
(2.8)
(3.2)
(3.5)
FO1L
127 ps
144 ps
159 ps
(2.8)
(23.2)
(3.5)
Includes std cell RC effects, intercell wires, and interrow/slot distribution bus. Bracketed data gives equivalent FO4 delays.
