Gate-Level Circuit Reliability Analysis: A Survey

<table>(a) A 2-input NAND gate and (b) its probability matrix <svg height="18.799999" id="M41" style="vertical-align:-4.77652pt" version="1.1" viewbox="0 0 23.5625 18.799999" width="23.5625" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
<g transform="matrix(.017,-0,0,-.017,.062,11.55)"><path d="M921 25v-25h-332v25q54 5 71.5 22t17.5 62v496l-252 -605h-27l-252 594v-465q0 -57 20 -79q19 -20 81 -25v-25h-234v25q58 6 75 20q16 15 16 63v469q0 41 -17 55q-16 14 -72 19v25h253l199 -472l201 472h252v-25q-56 -5 -72 -23q-16 -17 -16 -74v-428q0 -58 15 -77
q15 -20 73 -24z" id="x1D40C"></path></g>
<g transform="matrix(.012,-0,0,-.012,16.112,15.638)"><path d="M546 430q-14 -33 -37.5 -140t-38.5 -209q-29 -195 -156 -289q-29 -21 -70 -37t-78 -16q-62 0 -102.5 37t-40.5 69q0 27 26 48q19 15 25 -3q13 -43 46.5 -69t87.5 -26q55 0 83 21q29 22 50 65t43 140q14 64 29 163h-2q-55 -81 -149 -152q-59 -44 -102 -44q-23 0 -43.5 30
t-20.5 85q0 74 32.5 145.5t84.5 117.5q40 35 100 58.5t117 23.5q21 0 65 -8q30 -6 44 -6zM456 386q-40 16 -81 16q-29 0 -64 -13q-42 -17 -85 -97q-19 -36 -31.5 -86t-12.5 -86q0 -64 30 -64q20 0 52.5 21t60.5 52q74 81 95 123q26 62 36 134z" id="x1D454"></path></g>
</svg> (according to [<a href="/journals/vlsi/2014/529392/#B22">10</a>]).</table>

VLSI Design

Gate-Level Circuit Reliability Analysis: A Survey

Figure 2