Design of Smart Power-Saving Architecture for Network on Chip

Algorithm 4

VCs with SPS algorithm.

VCs with SPS Algorithm

Input: VCs clock, channel packet, arbiter signal and reset.

Output: channel packet, channel status

(1)   VC_count is integer and range is 1 ≤ VC_count ≤

(2)   VC_flag includes full flag and empty flag

(3)   initial VC_count and VC_flag

(4)   while (channel packet or arbiter signal be arrival) do

(5)  if (channel packet be arrival and full flag != 1)

(6)  {VC_count = VC_count + 1 and packet store in VCs}

(7)  if (arbiter signal be arrival and empty flag != 1)

(8)  {VC_count = and packet be read from VCs}

(9)   end while

(10) while (VC_count be change) do

(11)   if (VC_count = )

(12)  {assign full flag to 1}

(13)  else if (VC_count = 1)

(14)  {assign empty flag to 1}

(15)  else

(16)  {assign full flag and empty flag to 0}

(17) end while