VLSI Design

VLSI Design / 2014 / Article / Alg 5

Research Article

Design of Smart Power-Saving Architecture for Network on Chip

Algorithm 5

SPS algorithm.
SPS Algorithm
Input: system clock, channel packet, arbiter signal and reset.
Output: VCs clock
(1)   VCgroup is VCs group of 4 direction port
(2)   VCflag includes full flag and empty flag
(3)   Initial VCs clock and access VCs count and stage flag
(4)   follow LCR to arrangement all slots priority;
(5)    is VCs clock of each VCgroup //where
(6)   Example VCgroup = East port
(7)   initial = 0; //where
(8)   while (virtual channel be write) do
(9)  if (VCflag = empty)
(10)  = system clock}
(11)  If (VCflag = full flag)
(12)  = 0 and = system clock}
(13) end while
(14) while (virtual channel be read) do
(15) if (empty flag = 1)
(16)  = 0}
(17) end while

We are committed to sharing findings related to COVID-19 as quickly and safely as possible. Any author submitting a COVID-19 paper should notify us at help@hindawi.com to ensure their research is fast-tracked and made available on a preprint server as soon as possible. We will be providing unlimited waivers of publication charges for accepted articles related to COVID-19. Sign up here as a reviewer to help fast-track new submissions.