Journals
Publish with us
Publishing partnerships
About us
Blog
VLSI Design
Table of Contents
Special Issues
VLSI Design
/
2014
/
Article
/
Fig 12
/
Research Article
Design of Smart Power-Saving Architecture for Network on Chip
Figure 12
VCs power with clock diagram.
(a)
No clock-gating
(b)
Clock-gating
(c)
SPS