VLSI Design

VLSI Design / 2014 / Article / Fig 12

Research Article

Design of Smart Power-Saving Architecture for Network on Chip

Figure 12

VCs power with clock diagram.
531653.fig.0012a
(a) No clock-gating
531653.fig.0012b
(b) Clock-gating
531653.fig.0012c
(c) SPS

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